Title :
Survey of Scan Chain Diagnosis
Author :
Huang, Yu ; Guo, Ruifeng ; Cheng, Wu-Tung ; Li, James Chien-Mo
Author_Institution :
Mentor Graphics, Wilsonville, OR
Abstract :
Scan-based testing has proven to be a cost-effective method for achieving good test coverage in digital circuits. The Achilles heel in the application of scan-based testing is the integrity of the scan chains. The amount of die area consumed by scan elements, chain connections, and control circuitry varies with different designs. Typically, each scan cell in a scan chain has an index number. The cells in the chain are sequentially numbered from scan output to scan input, starting with 0. A chain pattern (sometimes called a flush pattern) is a pattern consisting of shift-in and shift-out operations without pulsing capture clocks. The purpose of chain patterns is to test scan chain integrity. A scan pattern (also known as a logic test pattern) is a pattern consisting of a shift-in operation, one or multiple capture clock cycles, and a shift-out operation. The purpose of scan patterns is to test system logic. The scan cells between the scan chain input and a scan cell´s scan input terminal are called the upstream cells of that scan cell. The scan cells between the scan chain output and a scan cell´s scan output terminal are called the downstream cells of that scan cell.
Keywords :
boundary scan testing; fault diagnosis; logic design; logic testing; chain connections; chain pattern; circuit design; control circuitry; digital circuits; flush pattern; logic test pattern; scan cell index number; scan chain diagnosis; scan elements; scan pattern; scan-based testing; Circuit faults; Circuit testing; Clocks; Digital circuits; Fault detection; Fault diagnosis; Graphics; Logic testing; System testing; Timing; chain diagnosis; chain failure; chain pattern; scan chain; scan pattern; survey;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2008.83