• DocumentCode
    1237895
  • Title

    A novel transition fault ATPG that reduces yield loss

  • Author

    Liu, Xiao ; Hsiao, Michael S.

  • Author_Institution
    Texas Instrum. Inc., Dallas, TX, USA
  • Volume
    22
  • Issue
    6
  • fYear
    2005
  • Firstpage
    576
  • Lastpage
    584
  • Abstract
    In this article, we have presented a novel constrained broadside transition ATPG algorithm to avoid overtesting functionally (sequentially) untestable transition faults. In some circuits, significantly more functionally untestable transition faults were identified. At the same time, more faults could be detected without incidental detection of functionally untestable transition faults. With a test set that reduces launching of transitions that are functionally impossible, we believe our method offers a practical solution to avoid overtesting these functionally impossible transitions, thus reducing yield loss. However, the runtime for our constrained ATPG is much longer than the conventional ATPG as a result of the constraint learning and construction process. Our future work concentrates on more-efficient constraint learning algorithms to reduce the over all ATPG runtime.
  • Keywords
    automatic test pattern generation; fault diagnosis; integrated circuit testing; ATPG algorithm; automatic test pattern generation; constraint learning algorithm; fault detection; transition fault; Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Delay; Design automation; Fault diagnosis; IEEE Press; Sequential circuits; Timing; Hardware I Computing Methodologies;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2005.126
  • Filename
    1541922