One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories

Spin transfer torque magnetic random access memory (STT-MRAM) has become one of the leading candidates for the next generation memory applications, thanks to its many attractive features. However STT-MRAM faces severe reliability challenges because of its intrinsic physical characteristics and the continuously scaling technology process. Thereby multi-bit error correction codes are considered indispensable techniques for STT-MRAM chips. Furthermore, considering the fact that STT-MRAM targets mainly to replace SRAM or (and) DRAM to be used as a working memory in the cache, main memory and embedded applications etc, high access speed is one of the most critical performance. In this paper, we propose to employ the one-step majority-logic-decodable (OS-MLD) codes to protect the STT-MRAM chips from failures. Their multi-bit error correction capabilities and simple encoding/decoding operations can enable STT-MRAM to be a reliable and high speed working memory. In addition, the optimized parallel decoder implementation of the OS-MLD codes accelerates further the decoding speed with little hardware overhead. A hybrid circuit with the DS(21,11) code and the STT-MRAM cell array has been implemented as a case study in the 28 nm technology node to illustrate the performance of the OS-MLD codes for STT-MRAM.