A high-linearity sampling technique for switched-current circuits

Author

Nairn, D.G.

Author_Institution

Dept. of Electr. & Comput. Eng., Queen´´s Univ., Kingston, Ont., Canada

Volume

43

Issue

1

fYear

1996

fDate

1/1/1996 12:00:00 AM

Firstpage

49

Lastpage

52

Abstract

Currently the dynamic range of switched-current circuits is much lower than that of switched-capacitor circuits. To address this problem, a current-mode sample-and-hold technique based on zero-voltage switching is presented. The technique avoids signal-dependent charge injection, thereby significantly increasing the sampler´s linearity. A sample-and-hold, based on the technique, was implemented using a 1.2 μm CMOS process and achieved 13-b linearity at sampling rates exceeding 50 MSamples/s, while dissipating only 5.3 mW from a 3.3 V supply

Keywords

CMOS analogue integrated circuits; sample and hold circuits; signal sampling; switched current circuits; 1.2 micron; 3.3 V; 5.3 mW; CMOS process; S/H method; SI circuits; ZVS; current-mode sample/hold technique; dynamic range; high-linearity sampling technique; switched-current circuits; zero-voltage switching; CMOS process; Dynamic range; Error correction; Linearity; Sampling methods; Signal sampling; Switched capacitor circuits; Switches; Switching circuits; Zero voltage switching;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.481474

Filename

481474