Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates

As an answer to the difficulties in improving the figures of merit of deeply-scaled CMOS devices, researchers have looked at alternative materials and technologies for implementing new devices that can overcome the limitations of CMOS. Graphene has emerged as one of the most promising candidates among these new materials, recent works have demonstrated the implementation of electrostatically-controlled p-n junctions that can serve as the basic primitive for a new class of compact, fast and energy-efficient graphene-based logic gates. In this work we revisit those gates from a different perspective, namely, as devices that can operate adiabatically, that is, that are able to reuse the dissipated energy. We show how to build the basic logic gates by appropriately interconnecting graphene based p-n junctions and characterize those adiabatic gates for power and performance. The comparison between these adiabatic gates and both adiabatic CMOS and their non-adiabatic graphene-based counterpart shows that the former can operate with 2X to 3X less average power, and about 4X better power-delay product.