• DocumentCode
    1239422
  • Title

    Performance trends in high-end processors

  • Author

    Sai-Halasz, George A.

  • Author_Institution
    Res. Div., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
  • Volume
    83
  • Issue
    1
  • fYear
    1995
  • fDate
    1/1/1995 12:00:00 AM
  • Firstpage
    20
  • Lastpage
    36
  • Abstract
    Based on a first order cycle time model performance trends and limits are projected for both bipolar and CMOS processors. The key in identifying trends is the understanding of the pivotal factors at any given stage of technology progression. One such parameter is the physical area of the processor. In coming technologies there will be opposite demands placed on the system´s area stemming from a need to reduce the proportion of interconnection capacitance and to send signals across the processor. Contrary to the usual perception, delays resulting from wiring capacitance decrease if processor area increases, while the minimization of signal travel times favors reducing area. The system size tradeoff in the case of bipolar processors is primarily determined by power density, while CMOS processor sizes are determined by wirability requirements. To achieve the full potential of CMOS, interconnections will have to be carefully planned. The performance limits of bipolar and room temperature CMOS uniprocessors are shown to be very similar. The highest performance technology on the horizon is liquid nitrogen temperature CMOS. Alternate technologies, based on III-V compound devices, or more exotic quantum structures, are not expected to play a role in future general-purpose high-end systems
  • Keywords
    CMOS digital integrated circuits; bipolar digital integrated circuits; integrated circuit interconnections; integrated circuit modelling; microprocessor chips; performance evaluation; CMOS ICs; bipolar ICs; first order cycle time model; high-end processors; interconnection capacitance; liquid nitrogen temperature CMOS; physical area; power density; signal travel times; system size tradeoff; wirability requirements; wiring capacitance; CMOS process; CMOS technology; Capacitance; Delay; Nitrogen; Power system interconnection; Semiconductor device modeling; Signal processing; Temperature; Wiring;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEEE
  • Publisher
    ieee
  • ISSN
    0018-9219
  • Type

    jour

  • DOI
    10.1109/5.362754
  • Filename
    362754