DocumentCode :
123943
Title :
Architecture of Effective High-Speed Network Stream Merger
Author :
Benacek, Pavel ; Kubatova, Hana ; Pu, Viktor
fYear :
2014
fDate :
27-29 Aug. 2014
Firstpage :
459
Lastpage :
464
Abstract :
This paper deals with the architecture for effective merging of high-speed network streams into one communication line. Networking hardware typically has more than one Ethernet port and if we want to transfer data via single communication bus (PCI-Express, for example) we need to merge all the Ethernet lines into one wide data stream. This paper discusses various approaches of dealing with the emerging issues related to very wide data busses and their alignment. The main contribution of this paper is the introduction of the architecture for merging of high-speed network streams as effective as possible. We use Virtex-7 equipped FPGA card to implement and test our architecture.
Keywords :
field programmable gate arrays; local area networks; peripheral interfaces; Ethernet lines; Ethernet port; FPGA card; PCI-Express; Virtex-7; communication line; high-speed network stream merger; networking hardware; single communication bus; Data transfer; Field programmable gate arrays; Hardware; Merging; Ports (Computers); Protocols; Throughput; 40 and 100 Gbps Ethernet; Effective High-Speed Network Stream Merging; FPGA;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design (DSD), 2014 17th Euromicro Conference on
Conference_Location :
Verona
Type :
conf
DOI :
10.1109/DSD.2014.25
Filename :
6927278
Link To Document :
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