Efficient High Speed Implementation of Secure Hash Algorithm-3 on Virtex-5 FPGA

Cryptographic hash functions have many security based applications, particularly in message authentication codes (MACs), digital signatures and data integrity. Secure Hash Algorithm-3 (SHA-3) is a new cryptographic hash algorithm that was selected on 2nd Oct ´12 after a five year public contest organized by the National Institute of Standards and Technology (NIST), USA. This paper provides a unique technique for the high speed implementation of SHA-3 on Field Programmable Gate Array (FPGA). In this implementation all the five steps of SHA-3 core are logically combined in such a way that it eliminates the intermediate states between these steps. The combination of the five steps results in 25 different equations, each of 64-bit word. These 25 equations have the same structure but different set of inputs and are implemented using the proposed hardware architecture. Xilinx Look-Up-Table primitives are used for the implementation of the proposed hardware architecture. This technique provides highest throughput i.e. 17.132Gbps and TPA (throughput/area) of 13.27 on Virtex-5 FPGA published to date.