State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System

In the design of Fault Tolerant Systems, some type of hardware redundancy is often used, Triple Modular Redundancy being one of the well known techniques of this type. Anyway, it must be taken into account that, after one of the copies of the implemented hardware fails, then it loses fault mitigation ability and continues in operation degraded to self-checking pair. In today´s dependable systems fault mitigation techniques are combined with techniques for the system repair and recovery. In FPGA-based systems the recovery process can be implemented by Partial Dynamic Reconfiguration process. In this paper, previously developed Fault Tolerant CAN Bus Control system and the FPGA partial reconfiguration process are combined to achieve the control system self-repairing ability. The synchronization process of the recovered circuit copy with the rest of the system which was operating while the faulty component reconfiguration was performed, is described in the paper.