Title :
Hierarchical Instruction Register Organization
Author :
Black-Schaffer, David ; Balfour, James ; Dally, William J. ; Parikh, Vishal ; Park, JongSoo
Author_Institution :
Comput. Syst. Lab., Stanford Univ., Stanford, CA
Abstract :
This paper analyzes a range of architectures for efficient delivery of VLIW instructions for embedded media kernels. The analysis takes an efficient filter cache as a baseline and examines the benefits from 1) removing the tag overhead, 2) distributing the storage, 3) adding indirection, 4) adding efficient NOP generation, and 5) sharing instruction memory. The result is a hierarchical instruction register organization that provides a 56% energy and 40% area savings over an already efficient filter cache.
Keywords :
cache storage; distributed shared memory systems; embedded systems; instruction sets; parallel architectures; NOP generation; VLIW instruction delivery; embedded media kernel; embedded processor architecture; filter cache; hierarchical instruction register organization; instruction memory sharing; Instruction fetch; Low-power design; RISC/CISC; VLIW architectures;
Journal_Title :
Computer Architecture Letters
DOI :
10.1109/L-CA.2008.7
