DocumentCode :
1239950
Title :
Hyperneural network-an efficient model for test generation in digital circuits
Author :
Rai, Suresh ; Deng, Weian
Author_Institution :
Dept. of Electr. & Comput. Eng., Louisiana State Univ., Baton Rouge, LA, USA
Volume :
45
Issue :
1
fYear :
1996
fDate :
1/1/1996 12:00:00 AM
Firstpage :
115
Lastpage :
121
Abstract :
This paper considers the problem of applying neural network for logic circuit testing and proposes an efficient method based on hyperneural network (HNN). The HNN uses an energy function that not only considers binary relations but also captures all higher order relations among N neurons. We illustrate the hyperneural concept using two formulations. First, a constraint energy function is defined and the gate model is obtained. Second, the Hopfield network is reformulated to generate the gate level hyperneural model. The gate level HNN are used to give a mathematical form to the digital circuit that, in turn, requires optimization techniques to solve the test generation problem. We have used ISCAS´85 benchmark circuits to illustrate the method. Results are compared with those obtained from PODEM, MODEM, and FAN
Keywords :
logic circuits; logic testing; neural nets; HNN; benchmark circuits; constraint energy function; digital circuit; energy function; gate model; hyperneural network; logic circuit testing; neural network; optimization techniques; test generation; Circuit faults; Circuit testing; Design automation; Digital circuits; Intelligent networks; Logic testing; Neural networks; Neurons; Notice of Violation; Random access memory;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.481493
Filename :
481493
Link To Document :
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