Bilayer Graphene Tunneling FET for Sub-0.2 V Digital CMOS Logic Applications

We propose a bilayer graphene (BLG) tunneling field-effect-transistor (TFET) suitable for digital CMOS logic circuits. The ultimate performance limit of this structure is evaluated by solving the quantum transport equations in nonequilibrium Green´s function framework. A bandgap opening is induced in BLG using both vertical electric field and top-bottom asymmetric chemical doping. To overcome the limitations of nonabrupt p-i-n junctions using practical process methods, source/drain regions are created using work-function engineered metal-graphene contacts. We evaluate the performance of BLG-TFET by taking doping gradient due to contact induced doping into account. Our BLG-TFET exhibits a subthreshold slope as low as 35 mV/dec, and ION/IOFF as high as 2910 for a supply voltage of 0.2 V. The proposed BLG-TFET shows promise for ultralow-power applications, particularly in low to medium speed applications.