A design support tool set for asynchronous circuits with bundled-data implementation on FPGAs

In this paper, we propose a design support tool set for asynchronous circuits with bundled-data implementation to implement them on commercial FPGAs easily considering a latency constraint. The design support tool set consists of six tools to automate constraint generation, timing verification, and delay adjustment for bundled-data implementation. In the experiments, we synthesize two circuits using the proposed tool set and compare area, performance, power consumption, and energy consumption with the synchronous counterparts.