Area minimization for floorplans

Author

Pan, Peichen ; Liu, C.L.

Author_Institution

Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA

Volume

14

Issue

1

fYear

1995

fDate

1/1/1995 12:00:00 AM

Firstpage

123

Lastpage

132

Abstract

In this paper we study the area minimization problem in floorplanning (also known as the floorplan sizing problem). For a given floorplan, the problem is to select a layout alternative for each subcircuit on a chip so as to minimize the chip area. Two area minimization methods for general floorplans are proposed. Both methods can be viewed as generalizations of the classical algorithm for slicing floorplans of Otten (1982) and Stockmeyer (1983) in the sense that they reduce naturally to their algorithm for slicing floorplans. Compared with the branch-and-bound algorithm of Wimer et al (1989), which does not have a nontrivial performance bound, our methods are provably better than an exhaustive method for all the examples we examined

Keywords

VLSI; circuit layout CAD; integrated circuit layout; minimisation; IC design; VLSI layout; area minimization problem; chip area; floorplan sizing problem; floorplan slicing; floorplanning; Circuits; Computer science; Minimization methods; Partitioning algorithms; Polynomials; Terminology; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.363119

Filename

363119