A scaled, high-performance (4.5 fJ) bipolar device in a 0.35 μm high-density BiCMOS SRAM technology

Author

Taft, R.C. ; Hayden, J.D.

Author_Institution

East Coast Labs. Inc., Salem, NH, USA

Volume

16

Issue

3

fYear

1995

fDate

3/1/1995 12:00:00 AM

Firstpage

88

Lastpage

90

Abstract

We present the performance improvements obtained both by scaling the Selectively Compensated Collector (SCC) BJT and by using a modified Current-Mode Logic (CML) gate configuration. Scaling the perimeter parameter by using the (tighter) bitcell design rules results in a /spl sim/30% reduction in parasitic capacitances, and a 23% lower power-delay product; reducing it from 48 fJ to 37 fJ. The greatest return comes from using a modified CML gate, which has an n-MOS current source. At a supply voltage of 1.1 V, and at 40 μA switching current, the minimum power-delay product of this CML gate is a silicon-substrate bipolar record 4.5 fJ.

Keywords

BiCMOS memory circuits; SRAM chips; bipolar transistors; current-mode logic; integrated circuit technology; logic gates; 0.35 micron; 1.1 V; 40 muA; BiCMOS SRAM technology; CML gate configuration; Si; current-mode logic; high-density SRAM technology; parasitic capacitances; perimeter parameter; power-delay product; scaled high-performance bipolar device; selectively compensated collector BJT; static RAM; BiCMOS integrated circuits; Delay; Doping; Implants; Logic devices; Logic gates; Parasitic capacitance; Random access memory; Resistors; Scalability;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.363233

Filename

363233