Systolic self-organizing lists under transpose

Systolic array architectures for self-organizing linear lists under the transpose update heuristic are presented. The first model has linear delay and restricts input on every other system cycle. The second system combines a systolic array with trees to provide logarithmic delay and input on every clock cycle. These preliminary designs can be the basis of hardware used to achieve high-speed lossless data compression for data communication and storage. On large files (greater than 40 kilobytes), our designs provide better compression than other systolic list compression schemes