Paralleled hardware annealing in multilevel Hopfield neural networks for optimal solutions

Author

Bang, Sa Hyun ; Chen, Oscal T C ; Chang, Josephine C F ; Sheu, Bing J.

Author_Institution

Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA

Volume

42

Issue

1

fYear

1995

fDate

1/1/1995 12:00:00 AM

Firstpage

46

Lastpage

49

Abstract

In a multilevel neural network, the output of each neuron is to produce a multi-bit representation. Therefore, the total network size can be significantly smaller than a conventional network. The reduction in network size is a highly desirable feature in large-scale applications. The procedure for applying hardware annealing by continuously changing the neuron gain from a low value to a certain high value, to reach the globally optimal solution is described. Several simulation results are also presented. The hardware annealing technique can be applied to the neurons in a parallel format, and is much faster than the simulated annealing method on digital computers

Keywords

Hopfield neural nets; optimisation; parallel processing; globally optimal solution; multi-bit representation; multilevel Hopfield neural networks; paralleled hardware annealing; simulation; Artificial neural networks; Computational modeling; Computer simulation; Hopfield neural networks; Intelligent networks; Neural network hardware; Neural networks; Neurons; Simulated annealing; Voltage;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.363542

Filename

363542