Title :
Clocked ratioed logic for implementing synchronous circuits in logic arrays
Author :
Mowchenko, J.T. ; Pong, M.Y.-M.
Author_Institution :
Dept. of Electr. Eng., Alberta Univ., Edmonton, Alta., Canada
fDate :
1/19/1995 12:00:00 AM
Abstract :
A new circuit style for implementing synchronous circuits in logic arrays is presented. The new style is a combination of dynamic and ratioed logic styles. Compared with existing logic arrays, the new style has a smaller layout area, competitive time performance, and lower power dissipation and switching currents
Keywords :
logic arrays; logic design; sequential circuits; clocked ratioed logic; layout area reduction; logic arrays; power dissipation reduction; switching current reduction; synchronous circuits; time performance;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19950095
