DocumentCode
1243646
Title
An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC
Author
Nakamura, Katsufumi ; Hotta, Masao ; Carley, L. Richard ; Allsot, D.J.
Volume
30
Issue
3
fYear
1995
fDate
3/1/1995 12:00:00 AM
Firstpage
173
Lastpage
183
Abstract
The design of a low-power 10 b, 40 Msample/s ADC integrated in a 0.8 μm multithreshold CMOS process is presented. The fully differential design employs parallel-pipelined ADC each using a combination of single- and multibit-per-stage pipelined architectures. The ADC, targeted for high-resolution video terminals and ultrasound scanning applications, achieves a nonlinearity-plus-quantization-error of ±1 LSB at 10 b, dissipates 85 mW from a single 2.7 V supply, and occupies an area of 1.9 mm by 2.1 mm
Keywords
CMOS integrated circuits; analogue-digital conversion; parallel processing; pipeline processing; video equipment; 0.8 micron; 10 bit; 2.7 V; 85 mW; A/D convertor; CMOS parallel-pipelined ADC; fully differential design; high-resolution video terminals; multibit-per-stage pipelined architecture; multithreshold CMOS process; ultrasound scanning applications; Analog-digital conversion; CMOS process; CMOS technology; Costs; Digital signal processing; Plastic packaging; Power dissipation; Sampling methods; Thermal resistance; Ultrasonic imaging;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.364430
Filename
364430
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