Title :
A 50 MHz eight-tap adaptive equalizer for partial-response channels
Author :
Wong, Caesar S H ; Rudell, Jacques C. ; Uehara, Gregory T. ; Gray, Paul R.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
3/1/1995 12:00:00 AM
Abstract :
A new architecture for digital implementation of the adaptive equalizer in Class IV partial-response maximum likelihood (PRML) channels employing parallelism and pipelining is described. The architecture was used in a prototype integrated circuit in a 1.2 μm CMOS technology to implement an eight-tap adaptive equalizer and Viterbi sequence detector which consumes a total of 70 mW from a 3.3 V supply operating at an input sampling rate of 50 MHz
Keywords :
CMOS digital integrated circuits; Viterbi detection; adaptive equalisers; digital magnetic recording; digital signal processing chips; magnetic disc storage; maximum likelihood detection; parallel architectures; partial response channels; pipeline processing; 1.2 micron; 3.3 V; 50 MHz; 70 mW; CMOS technology; Class IV PRML channels; Viterbi sequence detector; architecture; digital implementation; eight-tap adaptive equalizer; parallelism; partial-response channels; partial-response maximum likelihood channels; pipelining; prototype integrated circuit; Adaptive equalizers; CMOS integrated circuits; CMOS technology; Detectors; Integrated circuit technology; Maximum likelihood detection; Pipeline processing; Prototypes; Sampling methods; Viterbi algorithm;
Journal_Title :
Solid-State Circuits, IEEE Journal of
