Title :
A novel memory cell for multiport RAM on 0.5 μm CMOS Sea-of-Gates
Author :
Nii, Koji ; Maeno, Hideshi ; Osawa, Tokuya ; Iwade, Shuuhei ; Kayano, Shinpei ; Shibata, Hiroshi
Author_Institution :
System LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
fDate :
3/1/1995 12:00:00 AM
Abstract :
A novel memory cell circuit for multiport RAM on CMOS Sea-of-Gates (SOG) has been proposed. It contributes to the operation both at high speed and at low voltage. In addition, a fourfold read bit line technique is also proposed to reduce the access time. A multiport RAM generator with the novel memory cell has been developed. 2-port or 3-port RAM´s with flexible bit-word configurations are available. Test chips containing seven generated RAM´s were designed and fabricated on 0.5 μm CMOS SOG. The experimental results of the chip show that each RAM operates at over 1.4 V and that the address access time of the 3-port RAM (16b×256w) is 4.8 ns at 3.3 V
Keywords :
CMOS memory circuits; application specific integrated circuits; cellular arrays; random-access storage; 0.5 micron; 1.4 V; 3.3 V; 4.8 ns; 4096 bit; CMOS SOG; Sea-of-Gates; fourfold read bit line technique; high speed operation; low voltage operation; memory cell circuit; multiport RAM; Application specific integrated circuits; CMOS memory circuits; CMOS process; CMOS technology; Energy consumption; Low voltage; Random access memory; Read only memory; Read-write memory; Testing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
