DocumentCode
1244041
Title
Pipelined serial/parallel multiplier with contraflowing data streams
Author
Stojcev, Mile K.
Volume
27
Issue
25
fYear
1991
Firstpage
2361
Lastpage
2363
Abstract
An improved architecture of the Muller pipeline serial-parallel multiplier is presented. The proposed solution is based on the integration of two Muller cells into one. This modification has resulted in a reduction of the number of latches by 25% and an increase in the effectiveness of the architecture by eliminating interspersed zeros in the input data streams. An area-time criteria is used to compare the modified architecture with the Muller multiplier.
Keywords
cellular arrays; digital arithmetic; logic arrays; multiplying circuits; pipeline processing; Muller cells; area-time criteria; contraflowing data streams; modified architecture; pipelined multiplier; serial/parallel multiplier;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19911463
Filename
121360
Link To Document