Title :
On fault simulation for synchronous sequential circuits
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fDate :
2/1/1995 12:00:00 AM
Abstract :
We investigate the considerations to be employed in designing a fault simulator for synchronous sequential circuits described at the gate level. Three testing strategies and three methods of handling unknown state variable values are considered. Every combination of a test strategy and a method of handling unknown state variable values defines a different fault simulation procedure. Experimental results are presented to demonstrate the different fault coverage levels achievable by the various procedures. Based on these results, a fault simulation procedure that combines the various considerations is proposed
Keywords :
circuit analysis computing; fault diagnosis; logic testing; sequential circuits; ternary logic; fault coverage levels; fault simulation procedure; gate level; multiple observation time test strategy; single observation time test strategy; synchronous sequential circuits; test strategy; testing strategies; three-value logic; unknown state variable values; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Electrical fault detection; Logic circuits; Logic testing; Sequential analysis; Sequential circuits;
Journal_Title :
Computers, IEEE Transactions on
