Title :
Chip-level soft error estimation method
Author :
Nguyen, Hang T. ; Yagil, Yoad ; Seifert, Norbert ; Reitsma, Mike
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
This paper gives a review of considerations necessary for the prediction of soft error rates (SERs) for microprocessor designs. It summarizes the physics and silicon process dependencies of soft error mechanisms and describes the determination of SERs for basic circuit types. It reviews the impact of logical and architectural filtering on SER calculations and focuses on the structural filtering of soft radiation events by nodal timing mechanisms.
Keywords :
alpha-particle effects; elemental semiconductors; failure analysis; microprocessor chips; neutron effects; silicon; architectural filtering; chip level soft error estimation method; detected uncorrectable error; logical filtering; microprocessor designs; nodal timing mechanisms; single event upset; soft error rates; soft radiation events; structural filtering; Error analysis; Error correction; Filtering; Logic circuits; Logic devices; Physics; Silicon; Single event upset; Timing; Very large scale integration; Detected uncorrectable error (DUE); failure in time (FIT); logic derating (LD); mean time to failure (MTTF); silent data corruption (SDC); single event upset (SEU); soft error rate (SER); timing derating (TD);
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2005.858334
