Impacts of front-end and middle-end process modifications on terrestrial soft error rate

Author

Roche, Philippe ; Gasiot, Gilles

Author_Institution

Front-End Technol. & Manuf., STMicroelectron., Crolles, France

Volume

5

Issue

3

fYear

2005

Firstpage

382

Lastpage

396

Abstract

This paper reviews soft error rate (SER) mitigations with standard process modifications in up-to-date commercial CMOS SRAMs and flip-flops. Acting in the front-end or middle-end levels, the following technology options are mainly evaluated: well engineering, partially and fully depleted silicon-on-insulator (FD SOI), and MIM capacitors. SER robustness gains are compared for eight classical process options based on original and published data. The best hardening efficiencies for SRAMs arise from the addition of stacked capacitors and the use of partially depleted (PD) SOI. SER trends are also reported for FD SOI and dual gates.

Keywords

CMOS memory circuits; SRAM chips; alpha-particle effects; digital integrated circuits; flip-flops; neutron effects; silicon-on-insulator; CMOS SRAM; MIM capacitors; alpha particle effect; flip-flop; neutron effect; partially depleted SOI; silicon-on-insulator; standard process modifications; terrestrial soft error rate; CMOS process; CMOS technology; Error analysis; Fabrication; Flip-flops; MIM capacitors; Metallization; Neutrons; Robustness; Silicon on insulator technology; Alpha; MIM capacitors; SRAM; flip-flop; neutron; silicon-on-insulator (SOI); single-event latch-up (SEL); single-event upset (SEU); soft error rate (SER); well engineering;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2005.853451

Filename

1545898