Title :
Analog front-end architectures for high-speed PRML magnetic read channels
Author :
Pai, P.K.D. ; Brewster, A.D. ; Abidi, A.A.
Author_Institution :
Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA
fDate :
3/1/1995 12:00:00 AM
Abstract :
IC front-end architectures for a CMOS partial-response maximum likelihood magnetic read channel are re-examined. By organizing the front-end system components properly, several properties may be optimized; clock-recovery acquisition time can be minimized, sensitivity to ADC quantization noise may be reduced, and overall power and complexity may be minimized. Channel simulation reveals that efficient equalization may be carried out with an adaptive, continuous-time equalizer with only 4-poles, which increases drive packing densities over conventionally equalized channels. 1-/spl mu/m CMOS circuits necessary for realization of the desired 200 MHz front-end are designed, partially realized, and tested.<>
Keywords :
CMOS analogue integrated circuits; adaptive equalisers; analogue processing circuits; continuous time filters; magnetic recording; maximum likelihood detection; partial response channels; quantisation (signal); 1 micron; 200 MHz; ADC quantization noise; CMOS circuits; adaptive continuous-time equalizer; analog front-end architectures; clock-recovery acquisition time; drive packing densities; high-speed PRML magnetic read channels; partial-response maximum likelihood; Adaptive equalizers; CMOS integrated circuits; Circuit simulation; Circuit testing; Clocks; Integrated circuit noise; Magnetic noise; Noise reduction; Organizing; Quantization;
Journal_Title :
Magnetics, IEEE Transactions on
