Title :
Design and performance of a VLSI 120 Mb/s trellis-coded partial response channel
Author :
Rae, J.W. ; Christiansen, G.S. ; Siegel, P. ; Karabed, R. ; Thapar, H. ; Shih, S.
Author_Institution :
Div. of Storage Syst., IBM Corp., Rochester, MN, USA
fDate :
3/1/1995 12:00:00 AM
Abstract :
A VLSI trellis-coded partial-response (TCPR) codec module incorporating circuitry for three exploratory, improved trellis codes is presented. The architecture, implementation, and performance evaluation of a "partitioned" rate 8/10 matched-spectral-null (MSN) code are described in detail. The detector implementation uses a programmable, systolic architecture to realize a time-varying Add-Compare-Select (ACS) topology that rotates state-ACS assignments and periodically superimposes "auxiliary" survivor paths. The survivor memory unit requires only 3 bytes per interleave and is implemented using a two-stage, time-varying architecture combining register-exchange and traceback methods. The module was fabricated in 0.45 micron CMOS technology requiring less than 300 mW at 12 MB/sec. Selected experimental results for a variety of magnetic recording components are shown.<>
Keywords :
CMOS digital integrated circuits; VLSI; codecs; digital magnetic recording; digital signal processing chips; magnetic disc storage; partial response channels; systolic arrays; trellis codes; 0.45 micron; 12 MB/s; 300 mW; CMOS technology; VLSI; codec module; detector implementation; magnetic recording; programmable systolic architecture; rate 8/10 matched-spectral-null code; register-exchange methods; survivor memory unit; time-varying add-compare-select topology; traceback methods; trellis-coded partial response channel; two-stage time-varying architecture; CMOS technology; Circuits; Codecs; Convolutional codes; Decoding; Design methodology; Detectors; Partial response channels; Prototypes; Very large scale integration;
Journal_Title :
Magnetics, IEEE Transactions on
