DocumentCode
1245171
Title
An analytical programming model for the drain-coupling source-side injection split gate flash EEPROM
Author
Yu-Hsiung Wang ; Wu, Meng-Chyi ; Lin, Chrong-Jong ; Chu, Wen-Ting ; Lin, Yung-Tao ; Wang, Chung S. ; Cheng, Keh-Yung
Author_Institution
Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Taiwan
Volume
52
Issue
3
fYear
2005
fDate
3/1/2005 12:00:00 AM
Firstpage
385
Lastpage
391
Abstract
This paper presents a compact and accurate analytical model for evaluating the programming behaviors of the drain-coupling source-side injection (SSI) split-gate Flash memory. Starting with the bias-dependent and time-varying drain coupling ratio, a programming model is developed on the basis of the constant barrier height approximation and Lucky-electron model to express the full transient injection current, peak lateral electric field, and storage charge as functions of technological, physical, and electrical parameters. The extracted re-direction mean-free path of the SSI device is smaller than that of the channel hot-electron counterpart by one order of magnitude, which provides the physical intuition for the derived high injection efficiency of around 2/1000. The intrinsic coupling ratio depends only on technological parameters and is presented as the design index of the device. The usefulness of this model is its ability of constructing the complete operation plot of the time-to-program versus the programming voltage for various reliability windows and tunable technological parameters. Besides, the variance of the read current distribution of a memory array is also analytically predicted.
Keywords
flash memories; hot carriers; programming; semiconductor device models; SSI device; analytical programming model; barrier height approximation; channel hot electron; drain coupling ratio; drain-coupling flash EEPROM; hot carriers; intrinsic coupling ratio; lucky-electron model; memory array; peak lateral electric field; read current distribution; reliability windows; source-side injection flash EEPROM; split gate flash EEPROM; storage charge; transient injection current; tunable technological parameters; Analytical models; CMOS technology; Current distribution; EPROM; Flash memory; Functional programming; Nonvolatile memory; Semiconductor device modeling; Split gate flash memory cells; Voltage; Flash memories; hot carriers; programming model; source-side injection (SSI) programming;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2005.843883
Filename
1397988
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