DocumentCode :
1245185
Title :
The assignment heuristic for crossing reduction
Author :
Catarci, Tiziana
Author_Institution :
Dipartimento di Inf. e Sistemistica, Rome Univ., Italy
Volume :
25
Issue :
3
fYear :
1995
fDate :
3/1/1995 12:00:00 AM
Firstpage :
515
Lastpage :
521
Abstract :
Several applications use algorithms for drawing k-layered networks and, in particular, 2-layered networks (i.e. bipartite graphs). Bipartite graphs are commonly drawn in the plane so that all vertices lie on two parallel vertical lines, and an important requirement in drawing such graphs is to minimize edge crossings. Such a problem is NP-complete even when the position of the vertices on one layer is held fixed. This paper presents a heuristic, called the assignment heuristic, for edge crossing minimization in bipartite graphs, which works by reducing the problem to an assignment problem. The main idea of the assignment heuristic is to position simultaneously all the vertices of one layer, so that the mutual interaction of the position of all the vertices can be taken into account. We also show that the idea underlying the assignment heuristic can be effectively applied in other cases requiring edge crossing minimization
Keywords :
VLSI; circuit layout; directed graphs; heuristic programming; minimisation; 2-layered networks; VLSI chip design; assignment heuristic; bipartite graphs; crossing reduction; edge crossing minimization; k-layered networks; Bipartite graph; Design methodology; Interference; Remuneration; Routing; Upper bound; Very large scale integration; Wire;
fLanguage :
English
Journal_Title :
Systems, Man and Cybernetics, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9472
Type :
jour
DOI :
10.1109/21.364865
Filename :
364865
Link To Document :
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