Title :
NAND-type DRAM-on-SGT
Author :
Nakamura, Hiroki ; Sakuraba, Hiroshi ; Masuoka, Fujio
Author_Institution :
Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan
fDate :
3/1/2005 12:00:00 AM
Abstract :
In this brief, we propose a novel NAND-type DRAM-on-surrounding-gate transistor (SGT) architecture for high-density and low-voltage memory. The cell structure is composed of NAND-type DRAM vertically stacked on an SGT and an SGT-type capacitor. A cell size of 4F2 can be achieved. Since it operates as a gain cell, it is possible to obtain a sufficient amount of signal charge. The device was fabricated with a 0.8-μm lithography system.
Keywords :
DRAM chips; MOS memory circuits; low-power electronics; 0.8 micron; 3T-cell MOS RAM; NAND-type DRAM-on-SGT; SGT-type capacitor; cell structure; gain cell; high-density memory; lithography system; low-voltage memory; surrounding-gate transistor; Body regions; Capacitance; Capacitors; Equivalent circuits; Lithography; Memory architecture; Random access memory; Read-write memory; Silicon on insulator technology; Voltage; Gain cell; NAND-type DRAM; surrounding gate transistor (SGT);
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2004.842717
