DocumentCode :
1245366
Title :
Optimal wiresizing under Elmore delay model
Author :
Cong, Jason Jingsheng ; Leung, Kwok-Shing
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Volume :
14
Issue :
3
fYear :
1995
fDate :
3/1/1995 12:00:00 AM
Firstpage :
321
Lastpage :
336
Abstract :
In this paper, we study the optimal wiresizing problem under the Elmore delay model. We show that the optimal wiresizing solutions satisfy a number of interesting properties, including the separability, the monotone property, and the dominance property. Based on these properties, we have developed a polynomial-time optimal wiresizing algorithm for arbitrary interconnect tree structures under Elmore delay model. Extensive experimental results have shown that our wiresizing solution reduces interconnect delay by up to 51% when compared to the uniform-width solution of the same routing topology. Furthermore, compared to the wiresizing solution based on a simpler RC delay model our wiresizing solution reduces the total wiring area by up to 28% while further reducing the interconnect delays to the timing-critical sinks by up to 12%
Keywords :
VLSI; circuit layout CAD; circuit optimisation; delays; integrated circuit interconnections; integrated circuit layout; network routing; network topology; trees (mathematics); wiring; Elmore delay model; VLSI; arbitrary interconnect tree structures; dominance property; interconnect delay; monotone property; optimal wiresizing; routing topology; separability; timing-critical sinks; wiring area; Capacitance; Clocks; Delay; Design optimization; Integrated circuit interconnections; Routing; Steiner trees; Topology; Very large scale integration; Wire;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.365123
Filename :
365123
Link To Document :
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