TRACER-fpga: a router for RAM-based FPGA´s

Author

Chen, Ching-Dong ; Lee, Yuh-Sheng ; Wu, Allen C H ; Lin, Youn-Long

Author_Institution

Dept. of Comput. Sci., Tsing Hua Univ., Hsin-Chu, Taiwan

Volume

14

Issue

3

fYear

1995

fDate

3/1/1995 12:00:00 AM

Firstpage

371

Lastpage

374

Abstract

We describe a routing method for the design of a class of RAM-based field programmable gate arrays (FPGA). We model the interconnect resources as a graph. A routing solution is represented as a set of disjoint trees, each connecting all terminals of a net, on the graph. An expansion router is used for connecting a net. Initially, nets are connected independently of one another. Conflicts among nets over the usage of interconnect resources are resolved iteratively by a rip-up and rerouter, which is guided by a simulated evolution-based optimization technique. The proposed approach has been implemented in a program called TRACER-fpga. As compared with CGE and SEGA, TRACER-fpga in general requires fewer routing tracks at the expense of longer wiring delay. It is suitable for low-speed applications such as hardware emulation

Keywords

circuit CAD; circuit optimisation; delays; field programmable gate arrays; integrated circuit layout; logic CAD; network routing; trees (mathematics); RAM-based FPGAs; TRACER-fpga; disjoint trees; expansion router; hardware emulation; interconnect resources; rip-up and rerouter; routing method; routing solution; routing tracks; simulated evolution-based optimization technique; wiring delay; Design automation; Field programmable gate arrays; Integrated circuit interconnections; Joining processes; Programmable logic arrays; Routing; Switches; Table lookup; Tree graphs; Wiring;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.365127

Filename

365127