• DocumentCode
    1245598
  • Title

    Efficient diminished-1 modulo 2n + 1 multipliers

  • Author

    Efstathiou, Costas ; Vergos, Haridimos T. ; Dimitrakopoulos, Giorgos ; Nikolos, Dimitris

  • Author_Institution
    Dept. of Informatics, TEI of Athens, Greece
  • Volume
    54
  • Issue
    4
  • fYear
    2005
  • fDate
    4/1/2005 12:00:00 AM
  • Firstpage
    491
  • Lastpage
    496
  • Abstract
    In this work, we propose a new algorithm for designing diminished-1 modulo 2n+1multipliers. The implementation of the proposed algorithm requires n + 3 partial products that are reduced by a tree architecture into two summands, which are finally added by a diminished-1 modulo 2n+1 adder. The proposed multipliers, compared to existing implementations, offer enhanced operation speed and their regular structure allows efficient VLSI implementations.
  • Keywords
    VLSI; cryptography; multiplying circuits; residue number systems; tree data structures; VLSI design; computer arithmetic; fermat number transform; modulo 2n+1multiplier; residue number system; tree architecture; Algorithm design and analysis; Application software; Computer architecture; Convolution; Cryptography; Digital arithmetic; Digital signal processors; Roundoff errors; Signal processing algorithms; Very large scale integration; Fermat number transform; Index Terms- Modulo 2^n+1 multipliers; VLSI design.; computer arithmetic; residue number system;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2005.63
  • Filename
    1401868
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1245598