Testing complex couplings in multiport memories

Author

Nicolaidis, M. ; Alves, V. Castro ; Bederr, H.

Author_Institution

Reliable Integrated Syst. Group, Inst. Nat. Polytech. de Grenoble, France

Volume

3

Issue

1

fYear

1995

fDate

3/1/1995 12:00:00 AM

Firstpage

59

Lastpage

71

Abstract

In this paper, the effects of simultaneous write access on the fault modeling of multiport RAMs are investigated. New fault models representing more accurately the actual faults in such memories are then defined. Subsequently, a general algorithm that ensures the detection of all faults belonging to the new fault model is proposed. Unfortunately, the obtained algorithms are of O(n/sup 2/) complexity which is not practical for real purposes. In order to reduce the complexity of the former test algorithm a topological approach has been developed. Finally, a BIST implementation of one of the proposed topological algorithms is presented.<>

Keywords

built-in self test; fault diagnosis; integrated circuit testing; integrated memory circuits; multiport networks; network topology; random-access storage; BIST implementation; RAMs; complex couplings; fault modeling; multiport memories; simultaneous write access; topological approach; Application specific integrated circuits; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Multiprocessing systems; Random access memory; Software libraries; Ultra large scale integration; Very large scale integration;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.365454

Filename

365454