Cumulative balance testing of logic circuits

Author

Chakrabarty, Krishnendu ; Hayes, John P.

Author_Institution

Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA

Volume

3

Issue

1

fYear

1995

fDate

3/1/1995 12:00:00 AM

Firstpage

72

Lastpage

83

Abstract

We present a new test response compression method called cumulative balance testing (CBT) that extends both balance testing and accumulator compression testing. CBT uses an accumulated balance signature, and it guarantees very high error coverage (over 99%) for various error models. We demonstrate that the single stuck-line (SSL) fault coverage of CBT for many of the ISCAS 85 combinational benchmark circuits is 100%, and for all but one circuit, the fault coverage is over 99.5%. To make processor circuits self-testing, any existing accumulators and counters can be exploited to implement CBT. Its ease of implementation, provably high error coverage, and exceptionally high SSL fault coverage, even with reduced (nonexhaustive) test sets, make CBT suitable for the built-in self testing of processor circuits that require a guaranteed level of test confidence.<>

Keywords

built-in self test; combinational circuits; fault diagnosis; integrated circuit testing; logic testing; ISCAS 85 combinational benchmark circuits; accumulated balance signature; built-in self testing; cumulative balance testing; error coverage; error models; nonexhaustive test sets; single stuck-line fault coverage; test confidence; test response compression method; Application software; Automatic testing; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Counting circuits; Feedback; Logic circuits; Logic testing;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.365455

Filename

365455