A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter

Author

Nauta, Bram ; Venes, Ardie G W

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

Volume

30

Issue

12

fYear

1995

fDate

12/1/1995 12:00:00 AM

Firstpage

1302

Lastpage

1308

Abstract

A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm² in 0.8 μm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW

Keywords

CMOS integrated circuits; analogue-digital conversion; interpolation; ladder networks; 0.8 micron; 110 mW; 5 V; 8 bit; CMOS; analog bandwidth; circuit design; folding A/D converter; interpolating A/D converter; reference ladder; transresistance amplifier; Analog-digital conversion; Bandwidth; CMOS process; CMOS technology; Circuit synthesis; Interpolation; Pipelines; Power dissipation; Video signal processing; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.482155

Filename

482155