Title :
A digit-serial architecture for gray-scale morphological filtering
Author :
Lucke, Lori ; Chakrabarti, Chaitali
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN
fDate :
3/1/1995 12:00:00 AM
Abstract :
We present a digit-serial architecture for gray-scale morphological operations that operate on radix-2 redundant numbers. We present new implementations for a redundant number adder and a maximum unit that are used in the morphological dilation unit. These new designs have areas comparable to 2´s complement implementations but have significantly smaller latencies
Keywords :
VLSI; adders; digital arithmetic; digital signal processing chips; filtering theory; image processing; mathematical morphology; mathematical operators; 2´s complement implementations; digit-serial architecture; gray-scale morphological filtering; gray-scale morphological operations; image processing; maximum unit; morphological dilation unit; radix-2 redundant numbers; redundant number adder; Computer architecture; Delay; Feature extraction; Filtering; Gray-scale; Image processing; Logic functions; Machine vision; Morphological operations; Very large scale integration;
Journal_Title :
Image Processing, IEEE Transactions on
