An 800-MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 μm CMOS

Author

Tan, Loke Kun ; Roth, Edward W. ; Yee, Gordon E. ; Samueli, Henry

Author_Institution

Broadcom Corp., Irvine, CA, USA

Volume

30

Issue

12

fYear

1995

fDate

12/1/1995 12:00:00 AM

Firstpage

1463

Lastpage

1473

Abstract

An 800 MHz quadrature direct digital frequency synthesizer (QDDFS4) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc, The frequency resolution is 0.188 Hz with a corresponding switching speed of 5 ns and a tuning latency of 47 clock cycles. The chip is also capable of frequency and phase modulation. ECL-compatible output drivers are provided to facilitate I/O compatibility with other high speed devices. A high gain amplifier at the clock input enables the QDDFS4 chip to be clocked with ac-coupled RF signal sources with peak-to-peak voltage swings as small as 0.5 V. The 0.8 μm triple level metal N well CMOS chip has a complexity of 94000 transistors with a core area of 5.9×6.7 mm². Power dissipation is 3 W at 800 MHz and 5 V

Keywords

CMOS digital integrated circuits; UHF integrated circuits; circuit tuning; direct digital synthesis; frequency synthesizers; 0.8 micron; 12 bit; 3 W; 5 V; 5 ns; 800 MHz; ECL-compatible output drivers; I/O compatibility; QDDFS4 chip; ac-coupled RF signal sources; cosine waveforms; frequency modulation; frequency resolution; peak-to-peak voltage swings; phase modulation; power dissipation; quadrature direct digital frequency synthesizer; sine waveforms; spectral purity; switching speed; triple level metal N well CMOS; tuning latency; Clocks; Digital integrated circuits; Frequency control; Frequency synthesizers; Integrated circuit synthesis; Phase locked loops; Read only memory; Signal generators; Table lookup; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.482194

Filename

482194