3.5-Gb/s×4-ch Si bipolar LSI´s for optical interconnections

Author

Ishihara, Noboru ; Fujita, Shuichi ; Togashi, Minoru ; Hino, Shigeki ; Arai, Yoshimitsu ; Tanaka, Nobuyuki ; Kobayaski, Y. ; Akazawa, Yukio

Author_Institution

NTT LSI Labs., Atsugi, Japan

Volume

30

Issue

12

fYear

1995

fDate

12/1/1995 12:00:00 AM

Firstpage

1493

Lastpage

1501

Abstract

The 3.5-Gb/s, 4-ch transmitter and receiver LSI´s described here include a 5-to-1 multiplexer, a 1-to-5 demultiplexer, and analog PLL circuits that can generate high-speed clock (3.5 GHz) and retimed data. The chips make it possible to connect twenty pairs of 700-Mb/s electrical ports (14-Gb/s throughput) without any external elements even for the PLL. Both the transmitter and receiver LSI are 4.5-mm-square and are fabricated by a 40-GHz 0.5-μm Si bipolar process. The transmitter LSI dissipates 2.5 W, and the receiver LSI dissipates 3.6 W. Both have -4.5- and -2-V supply voltages

Keywords

bipolar analogue integrated circuits; demultiplexing equipment; integrated optoelectronics; large scale integration; multiplexing; multiplexing equipment; optical interconnections; optical receivers; optical transmitters; phase locked loops; silicon; -2 V; -4.5 V; 0.5 micron; 2.5 W; 3.5 GHz; 3.5 Gbit/s; 3.6 W; Si bipolar LSI chips; analog PLL; demultiplexer; electrical ports; high-speed clock data; multichannel interface circuits; multiplexer; optical interconnections; receiver; retimed data; transmitter; Circuits; Clocks; Large scale integration; Multiplexing; Optical interconnections; Optical receivers; Optical transmitters; Phase locked loops; Throughput; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.482197

Filename

482197