A CMOS gate array with 600 Mb/s simultaneous bidirectional I/O circuits

Author

Takahashi, Tatsuro ; Uchida, M. ; Takahashi, Tatsuro ; Yoshino, Rei ; Yamamoto, Manabu ; Kitamura, N.

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

Volume

30

Issue

12

fYear

1995

fDate

12/1/1995 12:00:00 AM

Firstpage

1544

Lastpage

1546

Abstract

A 610 kG gate array with simultaneous bidirectional I/O circuits has been developed using 0.5 μm CMOS four metal layer process technology. The number of I/O circuits is 608. A digitally-impedance-controlled low voltage swing output buffer circuit achieves high data throughput and low power. The maximum effective communication bandwidth is 600 Mb/s per pin, and the average power consumption of the I/O circuits is 12 mW per pin. A PLL can create the proper clock edge timing to latch data of 300 Mb/s with 120 ps of peak-to-peak jitter. Wide data band width can be obtained using a 1000 pin-class package for parallel processor systems

Keywords

CMOS logic circuits; buffer circuits; digital phase locked loops; logic arrays; 0.5 micron; 1000 pin-class package; 12 mW; 600 Mbit/s; CMOS gate array; digitally-impedance-controlled buffer; four metal layer process technology; high data throughput; low power operation; low voltage swing output buffer circuit; parallel processor systems; simultaneous bidirectional I/O circuits; Bandwidth; CMOS process; CMOS technology; Circuits; Clocks; Communication effectiveness; Energy consumption; Low voltage; Phase locked loops; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.482204

Filename

482204