DocumentCode :
1246671
Title :
Aliasing computation using fault simulation with fault dropping
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Volume :
44
Issue :
1
fYear :
1995
fDate :
1/1/1995 12:00:00 AM
Firstpage :
139
Lastpage :
144
Abstract :
It is generally thought that accurate analysis of aliasing requires non-fault dropping fault simulation. We show that fault dropping is possible when computing the exact aliasing of modeled faults for common output response compression circuits. The fault dropping process is most effective when the test set size is small. Extensions to large test sets are also considered. We present a fault simulation procedure that takes maximum advantage of fault dropping and present experimental results to support its effectiveness
Keywords :
combinational circuits; fault tolerant computing; logic testing; aliasing; combinational circuits; common output response compression circuits; fault dropping; fault simulation; output response compression; Analytical models; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Cities and towns; Computational modeling; Feedback circuits; Hardware; Linear feedback shift registers;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.368001
Filename :
368001
Link To Document :
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