High speed submicron BiCMOS memory

Author

Takada, Masahide ; Nakamura, Kazuyuki ; Yamazaki, Tohru

Author_Institution

Syst. ULSI Res. Lab., NEC Corp., Kanagawa, Japan

Volume

42

Issue

3

fYear

1995

fDate

3/1/1995 12:00:00 AM

Firstpage

497

Lastpage

505

Abstract

This paper reviews device and circuit technologies for submicron BiCMOS memories, especially for high speed and large capacity SRAM´s with 0.8 μm, 0.55 μm and 0.4 μm design rules. First, poly-silicon emitter structure and triple-well structure are described as key submicron BiCMOS device technologies for achieving high transistor performance and minimized process complexity, as well as high reliability. Next, submicron CMOS and BiCMOS inverter gate delays are compared. In addition, memory circuit techniques including BinMOS logic gates and bipolar sense amplifiers are discussed, respectively for ECL I/O asynchronous, TTL I/O asynchronous and super high speed synchronous submicron BiCMOS SRAM´s. Future prospects for submicron BiCMOS memories are also forecasted

Keywords

BiCMOS memory circuits; SRAM chips; emitter-coupled logic; integrated circuit technology; transistor-transistor logic; 0.4 to 0.8 mum; BinMOS logic gates; ECL I/O asynchronous technology; TTL I/O asynchronous technology; bipolar sense amplifiers; circuit technology; design rules; device technology; high reliability; high speed SRAM; inverter gate delays; large capacity SRAM; poly-silicon emitter structure; submicron BiCMOS memories; super high speed synchronous technology; triple-well structure; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Cache memory; Delay; Inverters; Logic devices; Logic gates; Paper technology; Random access memory;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.368046

Filename

368046