Title :
A high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications
Author :
Sung, J.M. ; Chiu, T.Y. ; Lau, K. ; Liu, T.M. ; Archer, V.D. ; Razavi, B. ; Swartz, R.D. ; Erceg, F.M. ; Glick, J.T. ; Hower, G.R. ; Krafty, S.A. ; LaDuca, A.J. ; Ling, M.P. ; Moerschel, K.G. ; Possanza, W.A. ; Prozonic, M.A. ; Long, T.P.
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
fDate :
3/1/1995 12:00:00 AM
Abstract :
A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 μm design rules (0.5 μm as one nesting tolerance) has achieved fl and fmax for npn bipolar (Ae=1×2 μm2) of 23 GHz and 24 GHz at Vce=3 V, respectively, with BVceo⩾5.5 volts, and βVA product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (Ae=1×2 μm2 ; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 Å, Leff=0.6 μm; Vth,nch =0.45 V; Vth,pch=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 μm; gate Leff=0.7 μm) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW
Keywords :
BiCMOS integrated circuits; emitter-coupled logic; integrated circuit technology; isolation technology; mixed analogue-digital integrated circuits; phase locked loops; 0.6 mA; 1 mum; 2 V; 2.1 mA; 23 GHz; 24 GHz; 3 V; 37 ps; 48 ps; 6 GHz; 60 mW; 70 ps; BEST2; BiCMOS phase-locked-loop; CMOS gate delay; ECL gate delay; bipolar enhanced super self-aligned technology; design rules; emitter width; extremely low parasitics; high performance BiCMOS technology; low-power mixed-signal applications; npn bipolar; process modules; total power consumption; witching currents; Analog integrated circuits; BiCMOS integrated circuits; CMOS process; Capacitance; Current measurement; Delay; Digital integrated circuits; Energy consumption; High speed integrated circuits; Phase locked loops;
Journal_Title :
Electron Devices, IEEE Transactions on
