A systematic layout-based method for the modeling of high-power HBT´s using the scaling approach

Author

Hajji, Rached ; Ghannouchi, Fadhel M. ; Kouki, Ammar B.

Author_Institution

Microwave Res. Lab., Ecole Polytech. de Montreal, Que., Canada

Volume

42

Issue

3

fYear

1995

fDate

3/1/1995 12:00:00 AM

Firstpage

528

Lastpage

533

Abstract

A systematic scaling approach for the modeling of high-power/large-size HBT´s is presented. This approach is based on: 1) identifying and characterizing the elementary cell, and 2) modeling the input/output interconnections using the device´s physical layout. The proposed approach reduces the optimization problem for the large-size device to the easier fitting of the lumped equivalent circuit of the elementary cell. It is shown that there is a good agreement between the predicted results, using the developed model, and the available measurements for different bias points. Such a modeling approach is particularly appealing for high-power applications where the large-signal characterization of large-size devices becomes a difficult task, particularly for on-wafer devices

Keywords

equivalent circuits; heterojunction bipolar transistors; lumped parameter networks; optimisation; power bipolar transistors; semiconductor device models; elementary cell; high-power HBTs; input/output interconnections; large-signal characterization; large-size device; lumped equivalent circuit; modeling; on-wafer devices; optimization; physical layout; scaling; Equivalent circuits; Frequency; Gain measurement; Helium; Heterojunction bipolar transistors; Integrated circuit interconnections; Performance evaluation; Power measurement; Predictive models; Scattering parameters;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.368050

Filename

368050