DocumentCode :
1246766
Title :
Resource-constrained system-on-a-chip test: a survey
Author :
Xu, Q. ; Nicolici, N.
Author_Institution :
Comput.-Aided Design & Test Res. Group, McMaster Univ., Hamilton, Ont., Canada
Volume :
152
Issue :
1
fYear :
2005
Firstpage :
67
Lastpage :
81
Abstract :
Manufacturing test is a key step in the implementation flow of modern integrated electronic products. It certifies the product quality, accelerates yield learning and influences the final cost of the device. With the ongoing shift towards the core-based system-on-a-chip (SOC) design paradigm, unique test challenges, such as test access and test reuse, are confronted. In addition, when addressing these new challenges, the SOC designers must consciously use the resources at hand, while keeping the testing time and volume of test data under control. Consequently, numerous test strategies and algorithms in test architecture design and optimisation, test scheduling and test resource partitioning have emerged to tackle the resource-constrained core-based SOC test. This paper presents a survey of the recent advances in this field.
Keywords :
logic testing; production testing; system-on-chip; accelerated yield learning; core-based system-on-a-chip; manufacturing test; modern integrated electronic products; product quality; resource-constrained system-on-a-chip test; test access; test architecture design; test architecture optimization; test resource partitioning; test reuse; test scheduling; testing time;
fLanguage :
English
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2387
Type :
jour
DOI :
10.1049/ip-cdt:20045019
Filename :
1404560
Link To Document :
بازگشت