Title :
A multi-standard video accelerator based on a vector architecture
Author :
Chouliaras, V.A. ; Nunez, J.L. ; Mulvaney, D.J. ; Rovati, F.S. ; Alfonso, D.
Author_Institution :
Dept. of electronic & Electr. Eng., Loughborough Univ., UK
Abstract :
A multi-standard video encoding coprocessor is presented that efficiently accelerates MPEG-2, MPEG-4 (XViD) and a proprietary H.264 encoder. The proposed architecture attaches to a configurable, extensible RISC CPU to form a highly efficient solution to the computational complexity of current and emerging video coding standards. A subset of the ISA has been implemented as a VLSI macrocell for a high performance 0.13 μm silicon process.
Keywords :
VLSI; computational complexity; integrated logic circuits; video coding; H.264 encoder; MPEG-2; MPEG-4; VLSI macrocell; computational complexity; extensible RISC CPU; multistandard video accelerator; multistandard video encoding coprocessor; vector architecture; video coding standard; Acceleration; Computational complexity; Computer architecture; Coprocessors; Encoding; Instruction sets; MPEG 4 Standard; Reduced instruction set computing; Very large scale integration; Video coding;
Journal_Title :
Consumer Electronics, IEEE Transactions on
DOI :
10.1109/TCE.2005.1405714
