DocumentCode
1247259
Title
A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation
Author
Reddy, G. Venkateshwar ; Kumar, M. Jagadesh
Author_Institution
Dept. of Electr. Eng., Indian Inst. of Technol., Delhi, India
Volume
4
Issue
2
fYear
2005
fDate
3/1/2005 12:00:00 AM
Firstpage
260
Lastpage
268
Abstract
In this paper, we present the unique features exhibited by a modified asymmetrical double-gate (DG) silicon-on-insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, i.e., a dual-material double-gate (DMDG) SOI MOSFET, exhibits significantly reduced short-channel effects (SCEs) when compared with the DG SOI MOSFET. SCEs in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage, and drain-induced barrier lowering. A model for the drain current, transconductance, drain conductance, and voltage gain is also discussed. It is seen that SCEs in this structure are suppressed because of the perceivable step in the surface-potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.
Keywords
MOSFET; nanoelectronics; semiconductor device breakdown; semiconductor device models; silicon-on-insulator; surface potential; Si; drain conductance; drain current; drain induced barrier lowering; dual-material double-gate nanoscale SOI MOSFET; short channel effects; surface potential profile; transconductance; two-dimensional analytical modeling; two-dimensional analytical simulation; Analytical models; CMOS technology; Conducting materials; MOSFET circuits; Predictive models; Semiconductor device modeling; Silicon on insulator technology; Threshold voltage; Transconductance; Two dimensional displays; Double gate (DG); IV model; drain-induced barrier lowering (DIBL); dual-material gate (DMG); silicon-on-insulator (SOI) MOSFET; two-dimensional (2-D) modeling;
fLanguage
English
Journal_Title
Nanotechnology, IEEE Transactions on
Publisher
ieee
ISSN
1536-125X
Type
jour
DOI
10.1109/TNANO.2004.837845
Filename
1406004
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