DocumentCode :
1247316
Title :
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations
Author :
Kim, Chris Hyung-il ; Jae-Joon Kim ; Mukhopadhyay, Saibal ; Roy, Kaushik
Author_Institution :
IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
Volume :
13
Issue :
3
fYear :
2005
fDate :
3/1/2005 12:00:00 AM
Firstpage :
349
Lastpage :
357
Abstract :
This paper presents a forward body-biasing (FBB) technique for active and standby leakage power reduction in cache memories. Unlike previous low-leakage SRAM approaches, we include device level optimization into the design. We utilize super high Vt (threshold voltage) devices to suppress the cache leakage power, while dynamically FBB only the selected SRAM cells for fast operation. In order to build a super high Vt device, the two-dimensional (2-D) halo doping profile was optimized considering various nanoscale leakage mechanisms. The transition latency and energy overhead associated with FBB was minimized by waking up the SRAM cells ahead of the access and exploiting the general cache access pattern. The combined device-circuit-architecture level techniques offer 64% total leakage reduction and 7.3% improvement in bit line delay compared to a previous state-of-the-art low-leakage SRAM technique. Static noise margin of the proposed SRAM cell is comparable to conventional SRAM cells.
Keywords :
CMOS memory circuits; SRAM chips; cache storage; integrated circuit design; integrated circuit noise; CMOS technology; SRAM cache memories; SRAM cells; combined device-circuit-architecture level techniques; device-circuit-architecture level technique; forward body biasing technique; leakage power reduction; nanoscale leakage mechanism; static noise margin; threshold voltage devices; transition latency; two dimensional halo doping profile; CMOS technology; Cache memory; Circuits; Design optimization; Doping profiles; Microprocessors; Nanoscale devices; Random access memory; Threshold voltage; Two dimensional displays; Forward body-biasing (FBB); SRAM; halo doping; leakage power; super high;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2004.842903
Filename :
1406041
Link To Document :
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