DocumentCode :
1247319
Title :
Low-power scan design using first-level supply gating
Author :
Bhunia, Swarup ; Mahmoodi, Hamid ; Ghosh, Debjyoti ; Mukhopadhyay, Saibal ; Roy, Kaushik
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume :
13
Issue :
3
fYear :
2005
fDate :
3/1/2005 12:00:00 AM
Firstpage :
384
Lastpage :
395
Abstract :
Reduction in test power is important to improve battery lifetime in portable electronic devices employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan-based testing, a significant fraction of total test power is dissipated in the combinational block. In this paper, we present a novel circuit technique to virtually eliminate test power dissipation in combinational logic by masking signal transitions at the logic inputs during scan shifting. We implement the masking effect by inserting an extra supply gating transistor in the supply to ground path for the first-level gates at the outputs of the scan flip-flops. The supply gating transistor is turned off in the scan-in mode, essentially gating the supply. Adding an extra transistor in only one logic level renders significant advantages with respect to area, delay, and power overhead compared to existing methods, which use gating logic at the output of scan flip-flops. Moreover, the proposed gating technique allows a reduction in leakage power by input vector control during scan shifting. Simulation results on ISCAS89 benchmarks show an average improvement of 62% in area overhead, 101% in power overhead (in normal mode), and 94% in delay overhead, compared to the lowest cost existing method.
Keywords :
combinational circuits; fault simulation; flip-flops; logic design; logic testing; low-power electronics; ISCAS89 benchmark; battery lifetime; combinational logic; fault simulation; first level supply gating; flip-flops; leakage power reduction; low power scan design; masking effect; portable electronic devices; power dissipation; reliability; scan based testing; signal transition; supply gating transistor; test cost reduction; test power reduction; vector control; Automatic testing; Batteries; Circuit testing; Combinational circuits; Costs; Delay; Electronic equipment testing; Flip-flops; Life testing; Logic testing; Low power test; scan design; supply gating;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2004.842885
Filename :
1406044
Link To Document :
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