Output interface with latching driver for LTS-SFQ circuits

We propose an output interface with a latching driver for single-flux-quantum (SFQ) circuits operating at 4.2 K. An optimum critical current density J_c of the latching driver was discussed, and a multichip module (MCM) structure with SFQ circuits and latching drivers was proposed for 40-Gb/s operation. To optimize J_c of the latching driver, we calculated the punchthrough probability of Nb-Al-AlO_x-Nb junctions and high-temperature superconductor (HTS) junctions. The Nb junction with a J_c of 45 kA/cm², which has a hysteresis of 44% for the latching operation, leads to a punchthrough probability lower than 10^-15 for an ideal ac-bias of 40 GHz. On the other hand, ramp-edge-type interface-modified junctions based on YBa₂Cu₃O_7-x have an optimum J_c of 60 kA/cm² that gives the smallest punchthrough probability lower than 10^-15 for an ideal ac-bias of 40 GHz without any shunt capacitance. Because the optimum J_c of 45 kA/cm² for the latching driver is too large to fabricate large-scale integrated SFQ circuits with the Nb junction, the MCM structure consisting of SFQ circuits and latching drivers with the optimum J_c is important to prepare 40-Gb/s SFQ systems. The J_c of 60 kA/cm² is a practical value for the HTS junctions, and use of the low-temperature superconductor (LTS)-HTS MCM structure is also one way to realize the high-speed SFQ systems.